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Job Description

Drives integration of analog and mixed signal IPs and highspeed interfaces into subsystems or analog components and partners with package and platform teams on analog integration. Supports pathfinding studies in silicon development and relays feedback to silicon and packaging team on analog integration and tradeoffs. Works include but not limited to synthesis, partition level floorplan, auto place and route, RC extraction and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, static timing and reliability analysis, clock generation, auto-place and route algorithms, floor planning, IP integration, and verification. You will work closely with RTL, Circuit and Mask Designers to troubleshoots a wide variety of difficult design issues and applied proactive intervention. Requires expansive knowledge and practical application of methodologies and physical design.

Guides the integration process from specification documentation to silicon tapeout and provides debugging support for analog functionality related debugs in the product. Possesses expertise in design verification flows, packaging effects, and integration flows to resolve integration challenges involved in mixed signal designs and deliver optimum performance of the overall circuit. Works closely with analog IP, SoC architecture, SoC design, package, and platform design functions to meet the analog specification for the product.

Qualifications

Bachelor/Masters of Science/Engineering degree in Electronic/Microelectronics Engineering or equivalent with 5 years of working experience in physical design or related field. Additional qualifications include: - Knowledgeable in digital logic design, VLSI CMOS custom circuit design - Strong programming skills in C/C++, or Perl/TCL or Phyton - Good communication and strong analytical skills - Strong team play

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.