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Google RTL Design Engineer in Tel Aviv-Yafo, Israel

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.

  • Experience in ASIC development with Verilog/SystemVerilog,SVa, VHDL or Chisel.

  • Experience with ASIC design verification, synthesis, timing/power analysis and DFT.

Preferred qualifications:

  • Knowledge of high performance and low power design techniques.

  • Knowledge of FPGA and emulation platforms, and of SOC architecture.

  • Knowledge of assertion-based formal verification.

  • Proficiency in a scripting language like Python or Perl.

  • Domain knowledge in one or more of the following areas: arithmetic units, bus architectures, processor design, accelerators and/or memory hierarchies.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. As part of our server chip design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You'll collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.

In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You'll collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

  • Define the block level design document such as interface protocol, block diagrams, transaction level flow, control registers, pipelines and etc.

  • Perform RTL development (coding and debug in Verilog, SystemVerilog, VHDL, UPF), function/performance simulation debug and Lint/CDC/FeV/PowerIntent checks.

  • Contribute to the chip level integration.

  • Participate in synthesis, timing/power closure and FPGA/silicon bring-up.

  • Participate in test plan and coverage analysis of the block and SOC-level verification.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy (https://careers.google.com/eeo/) and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) .

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