Google Coherent Interconnect Design Engineer, RTL in Tel Aviv-Yafo, Israel
Bachelor's degree in Computer Science or Electrical Engineering or equivalent practical experience.
Experience with design, implementation, and functional verification.
Experience with power efficiency and performance estimation automation.
Experience with multiple full SoC design cycles.
Master's or PhD degree in Computer Science or Electrical Engineering or equivalent practical experience.
Experience in ARM CPU coherent interconnect development.
Experience implementing engineering best practices (e.g., design reviews, code reviews, testing).
As a Coherent Interconnect Design Engineer, you will be responsible for microarchitecture, RTL design and implementation of cache coherent interconnect technology as part of Google’s data center SoC products. You will work alongside other RTL design, physical design and verification engineers and with direction from CPU and SoC architects and design leads during the microarchitecture, design, verification, and bringup phases of product development.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Manage the microarchitecture, design, and implementation of high-bandwidth, multi-core cache coherent interconnect RTL for SoCs that power Google's computing infrastructure.
Focus on coherency function as well as performance from the concept/planning stage through execution and closure.
Work with architecture, design, verification, and bringup teams to ensure product success.
Work jointly with CPU design SoC integration teams, ensuring successful integration of the CC interconnect into SoC.
Translate microarchitecture specifications to the physical design and power aware implementation in SystemVerilog.
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