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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform. Central to SCHIE’s mission is a highly programmable Data Processing Unit chip (DPU), which powers key aspects of the infrastructure. The DPU team is seeking a Senior Hardware Engineer, who will be responsible for delivering cutting-edge, high performance, low power, scalable and programmable silicon.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

As a Senior Hardware Engineer of the verification team, you will be responsible for independently creating leading edge verification environments and simulation testbeds, to validate and ensure functional correctness of innovative designs. Leveraging standard simulation tools, such as ns3 or OMNeT, you will develop traffic generators and implement accurate models of the protocols and devices to inform and influence the architectural and design directions for the Azure AI Infrastructure.

Responsibilities

• Creates robust, scalable, secure and extensible verification plans for the hardware engineering aspects of complex products or feature areas.

• Reviews documentation to help ensure that the appropriate test requirements and improvements are included in relevant hardware designs and specifications by applying an understanding of how complex features or products work under a variety of customer scenarios.

• Collaborates with other stakeholders to ensure test strategy is sound and meets constraints.

• Writes design verification test cases by identifying new tools, test methodologies, and/or best practices that include elements such as success metrics and tracking systems.

• Develops, reviews, and executes test plans for complex or large sized scope feature areas or products. Provides guidance to other engineers to execute test plans.

• Reviews the automated testing solutions with reusability, extendibility, and scalability, and helps with complex debugging within a product line. Seeks out opportunities for automation.

• Uses data/statistical analysis to identifyhighly complex problems or flaws that may affect a range of feature or product design changes. Identifiespossible solutions to novel and complex problems.

• Develops advanced prototype components for complex hardware for use in validation of new product features; provides guidance to other engineers in developing innovative features.

Qualifications

Required Qualifications:

• 7+ years of technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years of technical engineering experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years of technical engineering experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• Or equivalent Experience

• 7+ years of experience in ASIC/SoC verification with SV/UVM environments

• 2+ years experience in verifying Ethernet, TCP/IP, MAC/PCS, Networking blocks or equivalent experience

• 5+ years experience with modelling in C/C++ or System Verilog

Other Requirements

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Understanding of network protocols and traffic models

• Knowledge of formal verification, hardware emulation

• Knowledge of CPU, Cache Hierarchy, & SoC architecture/design

• 9+ years of experience in ASIC/SoC verification with SV/UVM environments

• 2+ years experience in OMNeT, NS3 or other network simulators or equivalent experience

• Team player with effective communication skills and the desire to take on diverse challenges

• In-depth knowledge of verification flows

• Clear understanding of constrained random verification process, functional coverage, assertion methodology & philosophy

Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year. Certain roles may be eligible for benefits and other compensation.

Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

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Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .