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Apple PHY Design Verification Engineer in San Diego, California

PHY Design Verification Engineer

San Diego,California,United States

Hardware

  • 2+ years of verification experience of wireless/wired communication block/subsystem.

  • Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.

  • Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.

  • Experience of using Matlab/C reference model and bit-accurate verification a plus.

  • Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.

  • Proficiency in shell and Perl scripting, Python skills a plus.

  • Experience of Palladium/FPGA validation a plus.

  • Should be a team player with excellent communication skills, self-motivated and well organized.

Description

  • Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. - Build block/subsystem level test benches with reference model, using best in class DV methodology. Architect test benches with maximum reusability in mind. - Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found. - Create and analyze block/subsystem level coverage model, and add test cases to increase coverage. - Support PHY subsystem validation using Palladium and/or FPGA.

Education & Experience

BS required, MSEE preferred.

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

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