Apple PHY Design Verification Engineer in San Diego, California
PHY Design Verification Engineer
San Diego,California,United States
2+ years of verification experience of wireless/wired communication block/subsystem.
Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
Experience of using Matlab/C reference model and bit-accurate verification a plus.
Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.
Proficiency in shell and Perl scripting, Python skills a plus.
Experience of Palladium/FPGA validation a plus.
Should be a team player with excellent communication skills, self-motivated and well organized.
- Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. - Build block/subsystem level test benches with reference model, using best in class DV methodology. Architect test benches with maximum reusability in mind. - Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found. - Create and analyze block/subsystem level coverage model, and add test cases to increase coverage. - Support PHY subsystem validation using Palladium and/or FPGA.
Education & Experience
BS required, MSEE preferred.
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