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Google Physical Design Engineer, Full-Chip/ASIC Implementation in Mountain View, California

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.

  • 5 years of physical design experience.

  • Experience with one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).

  • Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

Preferred qualifications:

  • Fundamentals of computer architecture and knowledge of Verilog/SystemVerilog.

  • Experience in top-level floorplanning, block integration

  • Experience in low power design Implementation including UPF/CPF, multi-voltage domains and power gating.

  • Experience with ASIC design flows and methodology of Physical design.

  • Understanding of Circuit design, device physics and deep submicron technology.

  • Effective skills with scripting languages such as Python, Tcl, and/or Perl.

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

In this role, you'll be part of a team responsible for delivering world class silicon for a range of applications and experiences.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

  • Develop all aspects of ASIC RTL2GDS implementation for high PPA designs.

  • Manage block and full-chip level physical implementation.

  • Define and implement innovative schemes to improve performance and power.

  • Work with cross functional teams to deliver the best quality results.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy (https://careers.google.com/eeo/) and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) .