Job Information
Cisco ASIC DESIGN FOR TEST ENGINEER - Acacia in Maynard, Massachusetts
The application window is expected to close on 1/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for Test group.
Your Impact
As a member of Acacia’s ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.
You will work with seasoned DFT engineers to implement and verify DFT.
- You will also interact with RTL/PD/STA/ATE, collaborating with them for a successful tape out.
Minimum Qualification:
BSEE or equivalent with + 8 years of experience or an MSEE or equivalent with + 6 years of experience, or PHD with + 3 years of experience in ASIC DFT flows and Implementation
Prior experience implementing scan control logic in RTL
Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVT
Prior experience with Synopsys/Mentor DFT tools
Preferred Qualifications:
Experience with scan compression and scan partitioning
Experience with MemoryBIST, eFuse, Repair and yield improvement techniques
Experience with JTAG Boundary Scan Insertion AC/DC
Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
TCL scripting experience to automate DFT flows
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