Cadence Design Systems, Inc. Principal Product Validation Engineer in Hsin Chu, Taiwan
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Candidates need to be familiare with synthesis and SoC design including STA, synthesis constraints and logic optimization and formal verification. Good at self-Learning & good team work and problem solving. Needs to be good at communication in English and Chinese.
BS/MS/PhD in EE/ECE/CS or related field with sufficient programming skills especially Python/Perl and Shell. Familiar with RC/Genus and Conformal tools will be a big plus too.
We’re doing work that matters. Help us solve what others can’t.
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence Design Systems, Inc.
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