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Job Description

The Extreme Scale Computing team is developing the next generation prototype solutions across Supercomputing, Memory, and heterogenous computing systems and is needing a Principal Packaging and Platform Hardware Architect to support our goals. If you have a strong interest to influence next-generation development of High Performance Computing Processor for Supercomputers, Graph Analytics/AI/Machine Learning SOCs or custom ASICs to partner with Xeon processor, this is the team to join.

The Principal Packaging and Platform Hardware Architect role will work with the pathfinding teams to define the development and alignment of major new packaging and system features to align with product timelines. The position will manage product/ POC needs and drive new technologies such as multi high die stacking architecture, memory technologies integration(DDR, LPDDR, HBM, other advance memories ), power delivery (Top side, on package voltage regulation ), Novel substrate materials need, IO chiplet solutions, FLI and SLI pitch scaling. This role will require cross division collaboration including business unit design, advanced IO technology development and engineering group design teams to drive detailed studies of proposed product features in advance of technology readiness. Candidate will also have the opportunity to evaluate and collaborate with external companies offering compelling assembly technologies.

Responsibilities will include:

Drive the package architecture definition and packaging technologies needed for next generation Intel products.

Develop long-term roadmaps for these features to minimize cost and maximize re-use across product lines

Align the assembly required to enable these features through pathfinding decision forums

Work with business unit and engineering team architects to create straw-man proposals for new packaging, assembly, and test features

Coordinate multi-disciplinary, multi-division teams internal and external to the company to evaluate and evolve these features until they provide a clear value proposition for Intel or are documented and dropped.

Coordinate alignment of these features to product families in ensuring any required building blocks reach maturity on the required timelines

Coordinate demonstrations of new features using test chips and custom test packaging

Qualifications

Minimum Qualifications: 15 year in package architecture and system design

package concept architectural expertise, including 2.5D and 3D packaging 2.5D and 3D Package assembly technology background preferred Cross-Industry next generation package technology understanding (Intel, Global, TSMC, Samsung and CMs) Board component layout experience Platform hardware architectural expertise Signal Integrity background, including package level and full channel Power integrity and power architecture at the multi-die, package, and board level Board technology and design integration deep experience Connector experience within-board and within rack, including high bandwidth and high speed signaling HPC platform level architecture and integration for various system level areas including signal integrity, power integrity, mechanical, thermal, board and network integration HPC rack level hardware architecture background preferred Thermal architecture integration at the package, board and rack level Power mgmt and clocking Co-packaged optics architecture Silicon photonics integration at package and platform level Memory integration and implementation at chip, pkg and board level.

Inside this Business Group

Enable amazing computing experiences with Intel Software continues to shape the way people think about computing – across CPU, GPU, and FPGA architectures. Get your hands on new technology and collaborate with some of the smartest people in the business. Our developers and software engineers work in all software layers, across multiple operating systems and platforms to enable cutting-edge solutions. Ready to solve some of the most complex software challenges? Explore an impactful and innovative career in Software.

Other Locations

US, AZ, Phoenix; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $186,760.00-$299,166.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.