Apple ASIC Design Engineer in Cupertino, California
ASIC Design Engineer
Santa Clara Valley (Cupertino),California,United States
Typically requires more than 8 years or more experience in digital design including RTL design experience
Experience in setting up Power Distribution architecture, power intent specification and validation methodology
Defining methodology and creating infrastructure to support FPGA based prototyping
Flow automation scripts using Perl/Python, Tcl, and shell scripts
Experience in Low Power is desired
Power user of industry standard RTL Design & Synthesis tools. Knowledge of Extraction and STA methodology and tools
Knowledge of best practices with respect to implementation of digital logic
Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, equivalence checking
Experience in DisplayPort or DSP is preferred
Understanding of Design Verification and the ability to write self-checking test suites
Experience in hands-on lab evaluation
Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
Work with systems team to understand the top level requirements of the digital functions and develop detailed specifications Implement the function in Verilog RTL to specification Perform unit level testing on the RTL function Support the DV team by writing self-checking tests as required Supporting all design integration activities like Lint, CDC, Synthesis & ECO Working with Physical Design Team on STA, physical, power and logical issues
Education & Experience
BSEE or MSEE, 5+ years of relevant experience
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