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The Microsoft Silicon Engineering and Solutions Team is seeking passionate, driven and intellectually curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas like Global Design Libraries, RTL & VIP Design, Design Verification, Validation, Simulation/Debug, Coverage and SoC integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our Design/Verification engineers so that they can deliver cutting-edge silicon solutions for Microsoft.  

Responsibilities

For all CAD roles, you will:   

• Be part of a central FE CAD team that drives common FE methodologies for SoC and IP design. 

• Be the expert in your domain and act in partnership with the execution team. 

• Independently own, drive and maintain Global Design/Verification Library components and manage releases to multiple SoC projects.

• Provide leadership to the design community for the CAD domain for which you are responsible. 

• Work with stakeholders across the Microsoft Silicon group to collect library design requirements. 

• Develop, enhance, and integrate common design and verification IP for organization-wide use.  

• Work with EDA vendors to adopt the most optimal solutions for silicon verification and design. 

• Mentor junior team members and summer interns. 

Qualifications

*Required:  * * *

• BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience.  

• 6+ years of experience in FrontEnd Digital Design and Verification.  

• Well-rounded and familiar with most Front-End Tools, Flows and Methodologies.  

• Strong Experience working with Verilog/SV/UVM based IP development.

• Experience with Logic Design Compilation, Simulation tools and flows

• Expertise in one of the following areas:

• Designcompile, elaboration and filelist/libraries handling.

• IP packaging, release and qualification

• IP integration

*Additional Preferred: * * *

• MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience. 

• 8+ years of relevant experience. 

• Strong background in owning and maintaining design/verification IPs End to end and handling releases.

• Good understanding with Standard cells, memories and behavioral modeling of design.

• Hands on expertise getting an IP through Frontend qualification (lint, cdc, rdc, synth, low power..) and successful release.

• Exposure to understand design functionality of existing IP, understand connectivity and apply incremental improvements.

• Good background and exposure to FE VLSI design cycle.  

• Hands on experience working with IP Design simulation debug flows.

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Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .