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Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are building a new team with front-end implementation skills and are looking for a  Principal Back - End Implementation Lead  to work on cutting-edge IP development as part of the expanding roadmap of the Semi-custom and Central IP Silicon team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

We’re committed to a diverse and inclusive workplace and strongly encourage applicants from all background and walks of life. Difference makes us better. 

Responsibilities

You will be the key link between back-end implementation and all front-end teams such as architecture, RTL, DV, DFT, while you execute individual tasks and provide technical leadership to a team of engineers conducting both RTL-to-PD validation as well as GDS hardening.

For some designs, your responsibility will include handoff to a physical hardening team. Pursuant to these tasks, you will be the leader in the enablement of quality RTL and collateral file drops to PD, and you will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-in-class PPA. You will also guide the hardening team in their execution and sign-off. Strong communication skills will be needed to coordinate with RTL, DFT, CAD and PD hardening teams.

For other designs, your responsibility will be to deliver hardened GDS. In this capacity, you may also be responsible for integrating customs macros (memories, PHYs, etc) while following their complex integration guidelines and working with the custom teams to understand trade-offs during this integration. You will be responsible for setting schedules and quality definitions for PD drops and milestones, while maximizing PPA and ensuring a smooth execution for all sign-off activities. In this role, you will be expected to coordinate with a diverse set of teams including RTL, DFT, CAD, integration, physical signoff, custom/analog teams, and program management.

You will be responsible for flow development, design automation, and correlation exercises against back-end flows. You are expected to work with limited direction, have attention to detail, and provide technical leadership to other engineers. You will also be expected to be able to provide crisp status of progress, issues, and risks on the program to the management team.

Qualifications

Required

• Bachelor of Science in Electrical or Computer Engineering

• 10+ years of experience in hardware design

• 8+ years of experience in Synthesis, Timing constraints, Front-end design checks and Power Performance Area (PPA) trade-offs

• 8+ years of experience in RTL-to-GDS activities, including PPA optimization, analog integration, and physical signoff activities

• Proficiency in collateral development including timing and synthesis constraints

• Proficiency in front-end design checks including LEC, Lint, Formal Equivalence, and CDC/RDC

• Proficiency in recent synthesis tool capabilities and methods for QoR improvement

• Proficiency in static timing analysis

• Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification

• Proficiency in translating physical design results into feedback for flow or RTL improvement

• Proficiency in Tcl, Perl, Python, shell programming

• Proficiency in providing technical direction to less-experienced engineers

Preferred

• Occasional travel

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .