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Position Summary

Samsung is a world leader in Memory, LCD and System LSI technologies that has the vision and commitment to invest in the future of technology – demonstrated by the $17B investment in the new 3nm Fab in Texas and the commitment to invest in dramatically expanding design activities across GPU, System IP and SoC Architecture. We are currently looking for exceptional software and hardware engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high volume products.

Role and Responsibilities

As a Senior SystemIP micro-architect, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP, memory controller and last level cache blocks. This is a senior role, tasked with interacting with the system architects, verification, performance/power and design implementation teams. You will be driving the RTL design, performance and power optimization, logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success. Help mentor junior engineers in the team

Key responsibilities include:

• Drive the timely development of custom coherent interconnect IP, memory controller and last level cache [LLC] blocks.

• Engage with the architects and help define next-generation Samsung coherent interconnects, memory controller and LLC.

• Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification

• Work with the verification team to verify the functionality and correctness of the design.

• Collaborate with implementation to achieve your timing and area.

• Produce quality RTL on schedule meeting PPA goals

• Engage with performance and power team on achieving performance and power goals.

• Partner with the physical design and CAD team to resolve implementation level details.

• Minimum requirements:

• PhD, Master’s Degree or Bachelor’s Degree, Computer Engineer with over 8+ years of experience.

• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs

• Deep understanding of memory controller or PHY design and experience in one or more memory technologies: DDR, LPDDR & HBM.

• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs

• Knowledge of system caches and directory snoop filter protocols.

• Familiarity with different on-chip network topologies: mesh, ring, crossbar.

• Experience in leading and mentoring a team of engineers.

• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols

• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

• Experience in leading and mentoring a team of engineers.

• Experience with a scripting language like Perl or Python.

• Knowledge of memory subsystem design including coherent cache design.

• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Skills and Qualifications

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.

• Proficient in AMBA, ACE, AXI, CHI protocols.

• Knowledge of memory controller and either coherent interconnect or cache design.

• Knowledge of PHY design.

• Knowledge of memory subsystem, coherency, directory snoop filter protocols.

• Familiarity with different on-chip network topologies: mesh, ring, crossbar.

• Experience in one or more memory technologies: DDR4/5, LPDDR & HBM.

• Experience with a scripting language like Perl or Python.

• Energetic, curiosity, and passion in logic design.

• Good written and verbal communication skills.

• Efficient digital design techniques.

• Knowledge of JEDEC memory standards.

Colorado: Compensation is expected to be between $214,916 to $333,119

NYC: Compensation is expected to be between $214,916 to $333,119

Washington State: Compensation is expected to be between $231,953 to $359,527

California: Compensation is expected to be between $231,953 to $359,527

Regular full-time employees (salaried or hourly) have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

#SARC

#ACL

*This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export controlled information or be eligible to receive a government authorization to access export-controlled information

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Samsung Electronics is a global leader in technology, opening new possibilities for people everywhere. Through relentless innovation and discovery, we are transforming the worlds of TVs, smartphones, wearable devices, tablets, digital appliances, and network systems, and the entire semiconductor industry with our memory, system LSI, foundry, and LED solutions. Samsung is also leading in the development of the Internet of Things through, among others, our Smart Home and Digital Health initiatives.

Since being established in 1969 , Samsung Electronics has grown into one of the world’s leading technology companies, and become recognized as one of the top global brands. Our network now extends across the world, and Samsung takes great pride in the creativity and diversity of its talented people, who drive our growth. To discover more, please visit our official newsroom at ( https://news.samsung.com/global/ ).