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Intel E-core SIP Enablement Engineer in Austin, Texas

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Come join Intel E-Core Soft IP Enabling Team. The E-Core team in addition to delivering CPU’s as Hard IP’s also delivers the CPU as a configurable Soft IP (SIP), that enables customers to harden the SIP to their requirements (PPA, aspect ratio etc) and target their foundry/process node of choice. The SIP enabling team is responsible for developing a reference design and associated flows and methodologies that showcases the best-in-class PPA that customers can achieve with minimal effort. In addition, the team is also responsible for implementing the CPU on external and internal process test chip shuttles to determine process entitlement and de-risking new technologies (both logic and process).

Who You Are

In this role, you will be responsible for all aspects of CPU backend implementation, from synthesis through GDS, including signoff verification, to achieve best in class PPA. This role will require excellent communication and cross functional skills. You will work with the Front-End Logic design team to identify opportunities to improve PPA and simplify the implementation of the CPU. In this role not only will you work on CPU backend implementation, but you will also be responsible for developing the design flow and identifying methodology improvements. You will have excellent scripting skills. You should be self-motivated and should be able to work in an open-ended environment.

You will be responsible for, but not limited to:

  • Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.

  • Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

  • Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

  • Analyze results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.

  • Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.

  • Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.

  • Optimizes CPU design to improve product level parameters such as power, frequency, and area.

  • Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must possess an MS degree in Electrical Engineering or other STEM related field and 4+ years of experience in backend implementation of high-performance VLSI designs.

Preferred Qualifications:

  • Solid knowledge of static timing analysis (STA) fundamentals

  • Knowledge of deep sub-micron process nodes, and successful product tape out

  • Experience with synthesis, Auto place and route (APR), extraction, STA, formal equivalence verification EDA tools

  • Should be well versed in Tools, Flow and Methodology development.

  • Expert knowledge in scripting languages such as Perl and TCL

  • Experience with Power optimization, DRV/LVS and Clocking a plus

  • Should be self-motivated and willing to work in an open ended environment

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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